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Lattice Semiconductor
FIFO Almost Full Threshold Register - Low (R/W)
Mnemonic: FIFOAFTL
POR Value = 00H
Application Support
Name
FIFO almost Full Low
bits [7:0]
Range
7:0
Description
FIFO almost Full Low bits : These bits set the loop back FIFO Almost Full
threshold [7:0] bits
FIFO Almost Full Threshold Register - High (R/W)
Mnemonic: FIFOAFTH
POR Value = 00H
Name
Rsvd [7:1]
FIFO almost Full High
bit [0]
Range
7-1
0
Description
Reserved.
FIFO almost Full High bit : This bit sets the loop back FIFO Almost Full
threshold [8] bit.
FIFO Almost Empty Threshold Register - Low (R/W)
Mnemonic: FIFOAETL
POR Value = 00H
Name
FIFO almost Empty Low
bits [7:0]
Range
7:0
Description
FIFO almost Empty Low bits : These bits set the loop back FIFO Almost
Empty threshold [7:0] bits
FIFO Almost Full Threshold Register - High (R/W)
Mnemonic: FIFOAETH
POR Value = 00H
Name
Rsvd [7:1]
FIFO almost Empty
High bit [0]
Range
7-1
0
Description
Reserved.
FIFO almost Empty High bit : This bit sets the loop back FIFO Almost
Empty threshold [8] bit.
RX Status Register (RO/COR)
Mnemonic: RXSTATUS
POR Value = 00H
Name
Rsvd [7:2]
rx_error
rx_fifo_error
Range
7:2
1
0
Description
Reserved.
rx_error : This bit is set high and latched if the rx_fifo_error signal is
asserted on TSMAC IP core pin. See Table 2-1 on page 14 for more infor-
mation on this TSMAC IP core signal.
rx_fifo_error : This bit is set high and latched if the rx_error signal is
asserted on TSMAC IP core pin. See Table 2-1 on page 14 for more infor-
mation on this TSMAC IP core signal.
IPUG51_03.0, December 2010
54
Tri-Speed Ethernet MAC User’s Guide
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